In source-synchronous systems, a data source endpoint sends data through a data channel to a data sink endpoint. In addition, the data source endpoint transmits a data strobe (e.g., a clock signal) over a data strobe channel to the data sink endpoint. The data sink uses the clock to latch or register the received data. As compared to the use of a system clock for transferring data, source-synchronous systems typically achieve considerably higher data rates. In a single-data-rate-source-synchronous system, the data is latched at the data sink on just one clock edge such as the rising edge. But in a double-data-rate (DDR) source-synchronous system, the data is latched on both the rising and falling edges. DDR data transmission is thus twice as fast as single data rate transmission at the same data strobe frequency.
Because of this speed advantage, double data rate signaling standards such as LPDDR4 (Low Power Double Data Rate 4) are quite popular for the reading and writing of data. For example, a microprocessor may write to a memory such as a dynamic random access memory (DRAM) by transmitting both a DDR data strobe and a data signal. It is conventional for the data strobe and the data signal to be carried on balanced paths. Not only are the on and off-chip routes for the data strobe and the data matched but the circuitry within the paths such as the drivers and terminations are also matched.
An example source-synchronous system 10 including a data source endpoint 101 such as an SOC and a data sink endpoint 102 such as a dynamic random access memory is shown in FIG. 1. System 10 is a double-data-rate system such that data source 101 transmits both a true data strobe that propagates over a true data strobe channel (DQST) to data sink 102 as well as a complement data strobe that propagates through a data strobe complement channel (DQSC) to data sink 102. A corresponding data signal propagates over a data channel (DQ). The electrical lengths of the data channel as well the true and complement data strobe channels is such that they may be treated as transmission lines having a characteristic impedance. To prevent reflections on these transmission lines, data receiver 102 includes on-die terminations each having an impedance that matches the characteristic impedance of the corresponding transmission lines. In particular, the DQST strobe channel ends in a termination 100, the DQSC strobe channel ends in a termination 105, and the DQ strobe channel ends in a termination 110. It is conventional that the DQSC, DQST, and DQ channels all have the same characteristic impedance and electrical length. In that regard, terminations 100, 105, and 110 all have a corresponding matching resistor R in parallel with a capacitor C that matches the termination impedances to the characteristic impedance for their corresponding channels. To further match the channels, a true data strobe driver 115, a complement data strobe driver 120, and a data driver 125 are all matching single-ended drivers comprising an inverter formed from a PMOS transistor P1 and an NMOS transistor M1.
System 10 works well at lower data rates. But as data rates are increased, power consumption goes up and the matching of the channels becomes more problematic. Accordingly, there is a need in the art for improved source-synchronous system architectures.